1. Field of the Invention
The invention relates in general to a method and a controller for accessing a first-in-first-out (FIFO) buffer, and more particularly to a method and a controller for accessing a FIFO buffer to reduce the transmission time required for data to be transmitted from one clock domain to another clock domain.
2. Description of the Related Art
In a system having different clock domains, a first-in-first-out (FIFO) buffer is often used to buffer the data while it is being transmitted from one clock domain to another, so as to perform the synchronization between the different clock domains. In a conventional FIFO buffer access scheme, only a full flag and an empty flag are used to indicate whether the FIFO buffer is full or empty. The data in the FIFO buffer is popped out only when the FIFO buffer is full. Thus, the time delay between the moment that the data is transmitted from one clock domain and the moment that the data is received in the other clock domain is very long. Therefore, the data transmission of the system is inefficient.
To reduce the transmission time for transmitting data from one clock domain to another, two extra flags, a half-full flag and a half-empty flag, are used in another conventional FIFO buffer data scheme. However, the control logic required for using the two extra flags is significantly more complex. Therefore, a method for accessing the FIFO buffer which is not only efficient but also has a low hardware complexity is highly desirable.